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Samsung’s new 2 nm foundry process to cut chip size by 17%

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Samsung Foundry Forum (SFF) 2024 was held in San Jose, California in June

A new contract chipmaking technology, dubbed the backside power delivery network (BSPDN), will reduce the size of a 2-nanometer chip by 17%, compared with the traditional front-end power delivery technology, said Samsung Electronics Co.’s foundry business executive on Thursday.

The BSPDN, Samsung is set to apply for mass production for the 2 nm process from 2027, also improves performance and power efficiency by 8% and 15%, compared with the chips with the front-end power delivery networks, Lee Sungjae, vice president and Foundry PDK Development Team at Samsung.

He explained about the technological prowess of the BSPDN in a keynote speech at Siemens EDA Forum 2024. It was the first time for a Samsung foundry business executive to give a detailed account of its BSPDN technology in public.

The BSPDN is called a next-generation chip foundry technology. It places power rails on the back of the semiconductor wafer to eliminate bottlenecks between the power and signal lines, allowing for making chips smaller.

Contract chipmakers are gearing up to adopt the advanced chipmaking process. Leading the pack, Intel plans to produce chips with BSPDN on the Intel 20A process, known as a 2 nm node, within the year. It dubbed its BSPDN technology as PowerVia.

TSMC, which controls 62% of the global foundry market, said it plans to introduce the BSPDN to its 1.6 nm and below process nodes around the end of 2026.

Samsung’s advanced foundry process node roadmap unveiled at Samsung Foundry Forum (SFF) 2024

Lee also unveiled the roadmap and performance of chips to be made with the next-generation gate-all-around (GAA) technology that Samsung adopted in 2022 for the first time in the world.

It plans to mass-produce 3 nm chips based on the second-generation GAA technology (SF3) in the second half of this year and deliver GAA on its upcoming 2 nm process.

SF3 has improved chip performance and power efficiency by 30% and 50%, respectively, while reducing the chip size by 35%, compared with the chips produced on the first-generation GAA process, Lee added.

By Jeong-Soo Hwang

hjs@hankyung.com 

Yeonhee Kim edited this article

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